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Physical Science International Journal, ISSN: 2348-0130,Vol.: 20, Issue.: 1


Manufacturing and Electrical Characterization of MOS Devices of Ultrathin Silicon Dioxide Layer


Anis M. Saad1*

1Al - Balqa Applied University, P.O. Box 4545, Amman - 11953, Jordan.

Article Information


(1) Dr. Bheemappa Suresha, Professor, Department of Mechanical Engineering, The National Institute of  Engg, Mysore, India.

(2) Dr. Christian Brosseau, Distinguished Professor, Department of Physics, Université de Bretagne Occidentale, France.


(1) Mario Alfredo Reyes-Barranca, Centro de Investigación y de Estudios Avanzados del IPN, México.

(2) Fauziyah Salehuddin,  Universiti Teknikal Malaysia Melaka UTeM),  Malaysia.

(3) Nenad Novkovski, Ss. Cyril and Methodius University, Macedonia.

Complete Peer review History: http://www.sciencedomain.org/review-history/27218


Metal-Oxide-Semiconductor–MOS devices presented here with thermally grown oxide layer of 3.04-5.92 nm thick were fabricated using p-type Si substrate. Capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics in frequency range of 10 kHz-100 kHz between 22 and 100 °C were measured in darkness. Current-voltage (I-V) was measured at Troom in darkness. C-V and G/ω-V at various frequencies revealed the energy distribution of MOS interface states. Current transport mechanisms in the device were studied and the I-V was generally characterised by Fowler-Nordheim and direct tunnel mechanisms of current carriers transport. Interface state density, flat-band voltages and frequency dispersion were extracted from C-V measurements. The frequency dispersion indicates the presence of either interface traps or laterally inhomogeneous distribution of defect centres near Si/SiO2 interface. The concentration of charged defects and their location at Si/SiO2 interface were calculated from frequency characterization. Small densities of interface traps < 2×1011 eV-1 cm-2 show that SiO2-Si interface has reliable qualities and its oxide may find applications in CMOS as dielectric gates. C-V of sample of dox = 4.14 nm was used to calculate at (22, 30, 50, 75, 100°C) the capacitance in accumulation mode, interface charge density, flat band voltage, threshold voltage and density of interface traps (in minimum position), Dit,= 0.3×1011-1×1011 cm-2. G/ω-V characteristics at Troom for sample of dox = 4.14 nm at 10 kHz, 50 kHz and 100 kHz were obtained. C-V of all 4 samples at Troom was also used to calculate the mentioned oxide properties. Two samples of dox = 3.04 nm and 4.14 nm were studied using X-ray photoelectron spectroscopy technique and evaluation of Si 2p peak was obtained for dox = 3.04 nm. Exact SiO2 thickness for all samples was measured by an ellipsometer.

Keywords :

Metal-oxide-semiconductor structures; ultrathin silicon dioxide layer; current-voltage characteristics; capacitance – voltage characteristics; conductance – voltage characteristics.

Full Article - PDF    Page 1-11

DOI : 10.9734/PSIJ/2018/44368

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